In semiconductor devices, cost reduction is required in addition to size reduction and thickness reduction. Therefore, in a semiconductor device of a BGA (ball grid array) structure and a CSP (chip size package) structure, a resin wiring substrate is used as a substrate to mount a semiconductor element. Normally, wiring patterns are formed on both surfaces of the resin wiring substrate, and in a semiconductor device using the resin wiring substrate, a semiconductor element is mounted on a surface of the resin wiring substrate, and solder balls for connecting to external connecting terminals are provided on the other surface of the resin wiring substrate. Also in both surfaces of the resin wiring substrate, a region excluding a bonding portion for connecting with the semiconductor element and a land portion for connecting solder balls is coated with a solder resist to protect wiring patterns and via portions.
In recent years, however, a very thin substrate having a thickness of about 0.3 mm or less has been used in such a semiconductor device, due to requirement for size reduction and thickness reduction. Therefore, a problem wherein such a semiconductor device is liable to warpage has arisen.
To cope with such a problem, Japanese Patent Application Laid-Open No. 3-40457 proposes a configuration for suppressing the warpage of a semiconductor device, wherein a semiconductor element mounted on a surface of a resin wiring substrate is entirely coated with a resin for encapsulation, and a region of the other surface corresponding to the region encapsulated by the resin is also encapsulated by the same resin.
However, since the thickness of a semiconductor element is normally at least 0.2 mm, and the resin must be thicker than the thickness of the semiconductor element, the above-described conventional configuration wherein the same resin films in thickness are formed on both surfaces of the substrate cannot sufficiently satisfy the requirement for thinning. There is also a problem wherein such a configuration cannot be applied to a package of a BGA type at all.
Japanese Patent Application Laid-Open No. 9-172104 proposes another configuration for suppressing the warpage of a semiconductor device. Specifically, there is proposed a configuration wherein the ratio of the coating area of a solder resist coating a surface of a resin wiring substrate to the coating area of a solder resist coating another surface of the resin wiring substrate is set within a range between about 1:1.3 and 1:1.7; and the ratio of the thickness of the solder resist coating a surface of the resin wiring substrate to the thickness of the solder resist coating another surface of the resin wiring substrate is set within a range between 3:1 and 5:1.
However, in such a configuration, the rigidity of the resin wiring substrate is elevated. Therefore, if a semiconductor element is mounted as a flip chip on the resin wiring substrate of such a configuration, thermal stress caused by the difference in the coefficients of thermal expansion between the resin wiring substrate and the semiconductor element acts on a connecting portion of the resin wiring substrate and the semiconductor element to easily cause poor connection at the connecting portion, and the breakdown of the vicinity of corners of the resin wiring substrate side of the semiconductor element (including inside the semiconductor element).